We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10734

3.1i Virtex MAP - FDS and FDRS are incorrectly packed into the same slice.


Keywords: Slice, mapped, packed, FDS, FDRS, set, reset, BY, SR, Init, Rev, logic, corruption

Urgency: Standard

General Description:
A case has been seen where MAP incorrectly packs an FDS and an FDRS into
the same slice. This has the effect of converting the FDS into an FDRS, as the
two registers share the Reset signal.

This problem will most likely be seen by Synplicity users, as their new synthesis
algorithms tend to generate more FDS registers.


This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 7.
AR# 10734
日付 08/19/2002
ステータス アーカイブ
種類 一般