General Description: Within the Synopsys tools, the constraints set_clock, set_input_delay and set_output_delay will carry forward into the Xilinx implementation tools through the NCF.
However, when instantiating a CLKDLL in the code, the FPGA Compiler II generates the following error:
Can't find clock - "clk_in" ' (for set_input_delay and set_output_delay).
ソリューション
The workaround is to pass the timing constraints through the UCF, using either a text editor or the Constraints Editor in the Design Manager.
In our tool:
"Set_clock property" is known as "Period." "Set_input_delay" property is known as "Offset in." "Set_output_delay" property is known as "Offset out."
NOTE: The problem and workaround will be the same for FPGA Express.