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AR# 10840

Synplify, Exemplar - How do I implement a Synchronous Reset in VHDL?

説明

General description: 

How do I implement a Synchronous Reset in VHDL in Synplicity or Exemplar?

ソリューション

VHDL 

 

No special attributes are necessary to implement a synchronous reset. Your VHDL code should look as follows: 

 

process (CLK) 

begin 

if (CLK'event and CLK='1') then 

if (RESET='1') then 

COUNT <= "00000000"; 

else 

COUNT <= COUNT + 1; 

end if; 

end if; 

end process;

 

Verilog 

 

No special attributes are necessary to implement a synchronous reset. Your Verilog code should look as follows: 

 

always @(posedge CLK) 

begin 

if (RESET) 

COUNT = 0; 

else 

COUNT = COUNT + 1; 

end;

AR# 10840
日付 05/14/2014
ステータス アーカイブ
種類 一般
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