We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1085

LCA2XNF may use unit delays (functional) in timing simulation flow


A user may observe in some cases, his timing simulation looks like a
functional simulation. This can be caused by LCA2XNF writing out an XNF file with no delay information annotated. LCA2XNF may do this if the LCA file has
DRC errors; it will use unit delays instead. If XSIMMAKE was run, this will
be reported in the XSIMMAKE.OUT file (WARNING 23).


Run a DRC check via XDE or Makebits to check if the LCA file is really OK.
If there are any errors, you must re-run PPR and/or adjust your design until
DRC check passes. PPR will sometimes produce LCA files that have DRC errors.
These errors are normally caught when Makebits is run, since Makebits runs
the DRC check automatically, but there is no such filter in Xsimmake.
AR# 1085
日付 04/05/2000
ステータス アーカイブ
タイプ 一般