NOTE: The SP7/SP8 fix for this problem may introduce a new problem in some designs that causes the timing score to diverge during routing. Please see (Xilinx Answer 11421) for further details.
This problem can be avoided in versions prior to SP7 and in SP8 if the patch for (Xilinx Answer 11421) is installed.
To work around this issue, you can disable DRC during BitGen by using the "-d" switch. Alternatively, you can use FPGA Editor to manually delete the loadless PWR/GND nets flagged by DRC. In version 4.1i, DRC will ignore these harmless nets by default.