General Description:
Although primitives for individual I/O standards exist for Virtex-II devices, FPGA Express does not recognize all I/O standards as primitives. The recommended method for implementation and synthesis to use the different I/O standards is to pass a constraint on the IBUF or the IBUFDS.
The examples below are resolutions in VHDL and Verilog that illustrate the passing of attributes in HDL. For information on passing I/O constraints through implementation, please refer to the IBUF, OBUF, IBUFDS, OBUFDS, and Constraints sections in the Libraries Guide, available at:
http://support.xilinx.com/support/library.htm
For information on Virtex-E I/O standard attribute passing, please see (Xilinx Answer 9849).
VHDL
The following example passes an IOSTANDARD attribute on an instantiated IBUF and IBUFDS. FPGA Express recognizes the IBUF, IBUFDS, and I/O buffers.
:
:
component IBUFDS is
port (I : in std_logic;
IB : in std_logic;
O : out std_logic);
end component;
component IBUF is
port (I : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD : string;
attribute IOSTANDARD of ibufds0 : label is "LVPECL_33";
attribute IOSTANDARD of ibuf0 : label is "AGP";
:
:
ibufds0 : IBUFDS port map (I=>ds0, IB => ds0_n, O=>ds0_ibufds);
ibuf0 : IBUF port map (I=>d0, O=>d0_ibuf);
Verilog
The following example passes an IOSTANDARD attribute on an instantiated IBUF and IBUFDS. FPGA Express recognizes the IBUF, IBUFDS, and I/O buffers.
:
:
IBUFDS ibufds0 (.I(d0), .IB(ds0_n), .O(ds0_ibufds));
//synopsys attribute IOSTANDARD "LVDS"
IBUF ibuf0 (.I(d0), .O(d0_ibuf));
//synopsys attribute IOSTANDARD "AGP"
:
:
AR# 10900 | |
---|---|
日付 | 05/21/2010 |
ステータス | アーカイブ |
種類 | 一般 |