General Description: Using FPGA Express, I am attempting to constrain a number of ports that have been assigned to a logic "one" or "zero". During the Translate step, however, the following error appears:
"ERROR:NgdBuild:397 - Could not find NET '<>' in design '<>'. NET entry is 'NET "<>" LOC = "<>";"
FPGA Express is not inferring the proper output buffers on these ports; therefore, they can not be constrained.
To work around this problem, instantiate the proper output buffer component, then port a signal to that buffer component that has been assigned to the desired logic level:
component OBUF port (I : in std_logic; O : out std_logic);
signal Zero : STD_LOGIC; signal One : STD_LOGIC;
Zero <= '0'; One <= '1';
u0 : OBUF port map (I => one, O => output_port_1); u1 : OBUF port map (I => zero, O => output_port_2);