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AR# 11169

Foundation ISE 3.1i SP6:HDL Converter:Converts files to Verilog even if VHDL is selected in the properties


Foundation, ISE, 3.1i, HDL, Converter

General Description:

When trying to convert an ABEL/AHDL file into VHDL using the HDL

Converter in Foundation ISE the output file created is always a Verilog file.


The only known workaround to this problem is to run the XPORT

program from the command line using the -VHDL switch.

AR# 11169
日付 01/06/2010
ステータス アーカイブ
種類 一般