AR# 11231


Precision Synthesis - How do I retain hierarchy in Precision?


Keywords: Precision, Synthesis, HDL, VHDL, Verilog, directive, constraint

Urgency: Standard

General Description:
How do I retain hierarchy in both my synthesis flow and implementation flow?


You can retain hierarchy in the synthesis flow by passing the "hierarchy" directive through the HDL code:

attribute hierarchy : string;
attribute hierarchy of comp_inst : label is "preserve";

//pragma attribute comp_inst hierarchy "preserve";

Precision currently does not support the passing of the KEEP_HIERARCHY implementation constraint. This constraint can be passed by the UCF.

For more information on the KEEP_HIERARCHY UCF constraint, please refer to the Constraints Guide:
AR# 11231
日付 04/20/2007
ステータス アーカイブ
種類 一般
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