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AR# 11507

HDL Bencher - When performing clock timing, how can I toggle input signals asynchronously in the waveform?


Keywords: HDL Bencher, simulation, testbench, clock, VHDL, Verilog, time, edge

Urgency: Standard

General Description:
HDL Bencher only allows waveform inputs to transition on the clock edge and not between clock edges when doing clock timing. Is there a way to toggle the inputs asynchronously?


This is possible if combinatorial timing is used instead of clock timing. The pattern wizard can be used to toggle the clock signal every "X" sections. You will then be able to toggle 2X times within the rising edges.
AR# 11507
日付 12/11/2006
ステータス アーカイブ
種類 一般