AR# 11532: 3.1i Virtex-II Speed Files - Improved delay modeling for the Virtex-II registered multiplier
AR# 11532
3.1i Virtex-II Speed Files - Improved delay modeling for the Virtex-II registered multiplier
説明
Keywords: MULT18X18S, MULT18X18, synchronous
Urgency: Standard
General Description: The Virtex-II registered multiplier (MULT18X18S) has only a single setup delay; however, the setup delay actually varies according to which pin is used to feed the multiplier.
The model was updated by the addition of distinct setup delays for different input pins.
NOTE: This fix affects ONLY the delay annotation of the MULT18X18S component. To access MULT18X18S in 3.1i software, you need to manually enable it in FPGA Editor.
This is fixed in the 4.1i release, where the MULT18X18S instantiated in EDIF is automatically implemented.