AR# 11643


Virtex-E Data Sheet - Certain LVDS pins (IO_LVDS_DLL for global clock) appear to be both N-side and P-side of a differential pair


The pin-out of the Virtex-E data sheet appears to show that certain LVDS pins, specifically the ones marked "IO_LVDS_DLL," can be used as both the N- and P-side of a differential I/O pair. 


For example, in the FG256 package, Pin N9 with function IO_DLL_L52P is the N-side of global differential clock pair 0 and it is also the P-side of differential pair 52. 


How is it possible for a pin to be both N and P? Is the data sheet wrong? If this is possible, how can differential pins exist in different banks? (For example, differential pair 52 of the FG256 package consists of Pin N9 in Bank 4 and Pin T8 in Bank 5.)


The data sheet is correct. 


The clock pins are special, as the regular GCK pins cannot be used as LVDS pins.  


The global clock input buffer may be combined with the adjacent IOB to form an LVDS or an LVPECL clock input buffer. The P-side resides in the GCLKPAD location, and the N-side resides in either of the adjacent IO_LVDS_DLLs, which can also be used as simple clocks or DLL feedbacks. 


IO_LVDS_DLL pins can be either N or P pins with respect to LVDS, but they can only be N for differential clocks. 


It is possible for differential pairs to be in different banks -- these pins fall into adjacent banks. If they are bidirectional I/O or outputs, the bank voltages must be the same. 


NOTE: For information on the pin number/pin name for a specific device/package combination, please refer to the pin-out table in the data sheet: 

AR# 11643
日付 05/14/2014
ステータス アーカイブ
種類 一般
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