Description: The Xilinx-Synopsys Interface (XSI) provides DesignWare Libraries that support arithmetic functions in XC4000 and XC5200 designs and high-level macro functions in XC7000 and XC9000 designs. The XSI also provides simulation libraries supporting VSS (Vital for M1). In order to use these libraries, you will need to analyze the DesignWare VHDL files after you install or upgrade your XSI software or upgrade your Synopsys tools. If you use VSS, you also need to analyze the VHDL simulation models.
ソリューション
1
(See Resolution 2 for XACT 5.2.1 instructions)
For Xilinx M1: =============
Be sure that the Synopsys and M1 software is properly installed and working on your system. Be sure the environment is correct including the $path, $XILINX, and $SYNOPSYS variables before beginning. You will also need write permissions to the $XILINX directory tree. Consult the Xilinx Install and Release Document or the Quickstart Guide, http://www.xilinx.com/txpatches/pub/documentation/M1/qstart.pdf, if you need more information about properly installing the software.
Analyzing the DesignWare libraries for Synthesis: ------------------------------------------------
To analyze the DesignWare files, change your current directory to each of the DesignWare library source directories for FPGA and/or CPLD (whichever is applicable) and run the install_dw.dc script, as follows.
Note: Substitute <device_family> with xc4000e, xc4000ex, xc4000l, xc4000xl, xc5200, xc7000, or xc9000 as follows.
cd $XILINX/synopsys/libraries/dw/src/<device_family>
dc_shell -f install_dw.dc
The previous commands analyze the encrypted DesignWare VHDL files and places the output files into the $XILINX/synopsys/libraries/dw/lib/<device_family> directory.
You should analyze the DesignWare library files if you use either the VHDL or Verilog HDL languages for synthesis.
If you recieve errors anlayzing the libraries above:
1. Warnings of the type : Warning: Can't read link_library file 'your_library.db'. (UID-3) are normal and can be ignored if no other errors were encountered.
2. Double check that the environment variables on your system are correct for both Synopsys and M1. Make sure the $SYNOPSYS environment variable is set to where the Synopsys software is installed, the $XILINX variable is set to where the M1 software is installed and the path contains the executables for M1 and Synopsys. Consult the Synopsys and M1 documentation for these and other correct environment settings.
3. Be sure you have write permissions to the directories where M1 is installed, particularly for the $XILINX/synopsys/libraries/dw/lib/* directories. If you are not sure, log in as root.
4. Check to see that both Synopsys and M1 was properly installed on the system. The Synopsys libraries are contained on the "Alliance Series CAE Interfaces" CD-ROM. If you are unsure whether all files were copied to the system, re-install the interface. Check Synopsys documentation to verify the Synopsys installation.
5. A VHDL compiler license is required to analyze the VHDL DesignWare libraries. Check to be sure that one exists and is availible to compile the libraries. (If you do not have a license, please see number 6 below.
6. If all else fails and the libraries still can not be analyzed, the analyzed libraries for various versions of M1 and Synopsys are on our FTP site. It is suggested that the debugging above to be taken place first because a problem with analyzing the libraries may indicate other problems with the system. The Designware libraries may also be quite large and take some time to download. If you wish to download the anlayzed libraries, see (Xilinx Solution 1166).
Analyzing the Simulation Libraries for Vital-VSS simulation: -----------------------------------------------------------
Analysis of the Vital-compliant libraries for the Synopsys VSS simulator consists of compiling the SIMPRIMS libraries (device independent) and the LOGIBLOX libraries (device independent) as well as analyzing the device family FTGS libraries.
First analyze the SIMPRIMS library for the VSS simulator.
A C-compiler needs to be referenced in you path in order to perform this step. Most UNIX systems should have a C-compiler defaultly installed on the system. Solaris users may experience problems since there is no default C-compiler installed with a typical installation. Please see (Xilinx Solution 2311) for information on setting up a C-compiler on Solaris systems.
Change directory to the SIMPRIMs library source directory and execute analyze.csh:
cd $XILINX/synopsys/libraries/sim/src/simprims
analyze.csh
Analyze.csh is a C-shell script which envokes Synopsys VHDLAN to compile the SIMPRIM libraries for the version of Synopsys running on your system.
Next step is to compile the LOGIBLOX libraries similarly to how the SIMPRIM libraries were compiled:
cd $XILINX/synopsys/libraries/sim/src/logiblox
analyze.csh
Finally, the device FTGS libraries need to be analyzed by Synopsys. To do so, change your current directory to the simulation library source directory of the device_family you wish to target and run the install_<device_family>.dc script. Substitute <device_family> with xc3000a, xc4000e, xc5200, xc7000, or xc9000 as follows.
cd $XILINX/synopsys/libraries/sim/src/<device_family>/ftgs
dc_shell -f install_<device_family>.dc
Repeat this step for all devices you plan on targeting.
The libraries are now comiled and analyzed and ready for use.
If errors were encountered while compiling or anlyzing the simulation libraries, please see (Xilinx Solution 2311) for debugging hints.
2
For XACT 5.2.1: ===============
Be sure that the Synopsys and XACT 5.2.1 software is properly installed and working on your system. Be sure the environment is correct including the $path, $XACT, $DS401, and $SYNOPSYS variables before beginning. For more information on properly installing the software, please consult the XACT Installation Guide, http://www.xilinx.com/txpatches/pub/documentation/xactstep6/install.pdf
Analyzing the Designware Libraries for Synthesis: ------------------------------------------------
To analyze the DesignWare files, change your current directory to each of the Designware library source directories for FPGA and run the install_dw.dc script, as follows.
Note: Substitute <device_family> with xc3000, xc4000, or xc4000e as follows.
cd $DS401/synopsys/libraries/dw/src/fpga/<device_family>
dc_shell -f install_dw.dc
This should be followd by analyzing the EPLD DesignWare libraries.
cd $DS401/synopsys/libraries/dw/src/epld
dc_shell -f install_dw.dc
The previous commands analyze the encrypted DesignWare VHDL files and place the output files into the $DS401/synopsys/libraries/dw/lib/fpga and $DS401/synopsys/libraries/dw/lib/epld directories.
You should analyze the DesignWare library files if you use either the VHDL or Verilog HDL languages for synthesis.
If you recieve errors anlayzing the libraries above:
1. Warnings of the type : Warning: Can't read link_library file 'your_library.db'. (UID-3) are normal and can be ignored if no other errors were encountered.
2. Double check that the environment variables on your system are correct for both Synopsys and XACT. Make sure the $SYNOPSYS environment variable is set to where the Synopsys software is installed, the $XACT variable is set to where the XACT software is installed, the $DS401 variable is set to where the XSI software is installed and the path contains the executables for XSI, XACT, and Synopsys. Consult the Synopsys and XACT documentation for these and other correct environment settings.
3. Be sure you have write permissions to the directories where XSI is installed, particularly for the $DS401/synopsys/libraries/dw/lib/* directories. If you are not sure, log in as root.
4. Check to see that both Synopsys and XACT was properly installed on the system. The Synopsys libraries are contained in the DS-401 package on the XACT 5.2.1 workstation CD-ROM. If you are unsure whether all files were copied to the system, re-install the interface. Check Synopsys documentation to verify the Synopsys installation.
5. A VHDL compiler license is required to analyze the VHDL DesignWare libraries. Check to be sure that one exists and is availible to compile the libraries. (If you do not have a license, please see number 6 below.
6. If all else fails and the libraries still can not be analyzed, the analyzed libraries for XACT and various versions of Synopsys are on our FTP site. It is suggested that the debugging above to be taken place first because a problem with analyzing the libraries may indicate other problems with the system. The DesignWare libraries may also be quite large and take some time to download. If you wish to download the anlayzed libraries, see (Xilinx Solution 1166).
Analyzing the Simulation Libraries for VSS Simulation: -----------------------------------------------------
To analyze the VSS model files, change your current directory to the simulation library source directory for each Xilinx family you are using and run the install_family. dc script. Substitute <device_family> with xc3000, xc4000, xc4000e, or xc5200 as follows.
cd $DS401/synopsys/libraries/sim/src/<device_family>
dc_shell -f install_<device_family>.dc
Then anlyze the EPLD Simulation Libraries.
cd $DS401/synopsys/libraries/dw/src/epld
dc_shell -f install_xc7000.dc
Note: The simulation files for the XC7000 family are located in the $DS401/synopsys/libraries/dw/src/epld directory.
The libraries are now anlayzed and ready for use.
If errors were encountered while compiling or anlyzing the simulation libraries:
1. Warnings of the type : Warning: Can't read link_library file 'your_library.db'. (UID-3) are normal and can be ignored if no other errors were encountered.
2. Make sure the $DS401 environment variable is set properly. $DS401 should be pointing to the top of the XSI software tree.
3. Make sure the $SYNOPSYS enviroment variable is set properly. Additionally, make sure it is pointing to Synopsys 3.3a, or later.
4. Make sure that you have write permissions/ownership of the directories and files in the $DS401 tree. If you are not sure of this, log in as root.
5. If all else fails, the VSS simulation libraries may be obtained from the Xilinx FTP site. see (Xilinx Solution 1166) for details.
3
The M1 XSI XDW and XACT XSI XBLOX DesignWare libraries are written only in VHDL. If you do not have a VHDL-compiler license, an analyzed version of the XDW or XLBOX libraries can be downloaded from the Xilinx FTP site (Xilinx Solution 1166).