AR# 11894

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Foundation 3.1i/LogiBLOX - MUX8_5: Input signals are being optimized away

説明

General Description: 

The MUX8_5 input signals I am using are being optimized away. I am using a Foundation Schematic Editor and targeting an XC95144 part.

ソリューション

To work around this problem, use the following VHDL: 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

 

entity mux8_5is 

port ( 

one: in STD_LOGIC_VECTOR (7 downto 0); 

two: in STD_LOGIC_VECTOR (7 downto 0); 

three: in STD_LOGIC_VECTOR (7 downto 0); 

four: in STD_LOGIC_VECTOR (7 downto 0); 

five: in STD_LOGIC_VECTOR (7 downto 0); 

output: out STD_LOGIC_VECTOR (7 downto 0); 

sel: in STD_LOGIC_VECTOR (2 downto 0) 

); 

end mux8_5; 

 

architecture mux8_5_arch of mux8_5 is 

begin 

 

 

process (SEL, one, two, three, four, five) 

begin 

case SEL is 

when "000" => output (7 downto 0)<= one(7 downto 0) ; 

when "001" => output (7 downto 0) <= two (7 downto 0) ; 

when "010" => output (7 downto 0) <= three (7 downto 0) ; 

when "011" => output (7 downto 0) <= four (7 downto 0) ; 

when "100" => output (7 downto 0) <= five (7 downto 0) ; 

when others => NULL; 

end case; 

end process; 

 

 

end mux8_5_arch;

AR# 11894
日付 03/05/2014
ステータス アーカイブ
種類 一般
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