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AR# 12301

5.1i Timing Analyzer/TRCE (Trace) - The TIG constraint is not properly applied to the design

説明

General Description:

My FROM:TO TIG constraint is not being properly applied to my design. Why is this happening?

ソリューション

This problem is caused by path intersections between multiple TIGs.

To work around this issue, combine all TIGs that have common destination groups. This will produce the correct behavior.

For more information, please see (Xilinx Answer 9297).

AR# 12301
日付 01/18/2010
ステータス アーカイブ
種類 一般
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