General Description: My design contains an instantiated VHDL/Verilog module on a schematic drawing. I select the module symbol and the "Push Into Symbol" option. The source then opens in the Project Navigator window, but it is minimized.
The Project Navigator window does not open in the foreground on Windows 98/Windows 2000 because of a change to these operating systems. Microsoft has added a "foreground lock timeout value". This lock timeout is the amount of time following user input that the system will allow another application to force itself to the foreground.
ECS is sending the command to Project Navigator to open the specified VHDL file in the HDL Editor; Project Navigator then attempts to force itself into the foreground window (by calling SetForegroundWindow), but this call fails because the foreground lock timeout value is not "0".
If you change the system value of the lock timeout to "0", applications will behave the same in Windows 2000/98 as they do on Windows NT.
Note 1: Editing the "Lock Timeout" value is a global change -- it may affect other applications on the system that were specifically programmed to use this option.
Note 2: Other Xilinx applications (Timing Analyzer, FPGA Editor, etc.) are always launched in the background on Windows 98 and Windows 2000. Changing the Lock Timeout value to "0" should allow these programs to be launched in the foreground.