Where do I find documentation for a pipelined multiplier?
MULT18X18S is a pipelined multiplier, and it is a registered (or 1-pipeline) version of MULT18X18.
A brief description of this library component can be found in the Libraries Guide of the 4.1i Software Manual, located at:
MULT18X18S components are available in software versions 4.1i and later. The following VHDL/Verilog examples illustrate MULT18X18S instantiation.
port (A : in STD_LOGIC_VECTOR (17 downto 0);
B : in STD_LOGIC_VECTOR (17 downto 0);
C : in STD_ULOGIC ;
CE : in STD_ULOGIC ;
P : out STD_LOGIC_VECTOR (35 downto 0);
R : in STD_ULOGIC );
module MULT18X18S (P, A, B, C, CE, R);
output [35:0] P;
input [17:0] A;
input [17:0] B;
input C, CE, R;