When I click the ILA button in FPGA Editor, not all of the signals are connecting to the ILA core in the list window.
This is due to the mapper. If a signal going into the core is immediately registered, and the logic driving that signal is combinatorial, the LUT and FF will occasionally be combined into the same slice. When this happens, there is no net name (as it is internal to the slice).
To avoid this problem, change probing point into output of FF so that all the connections require at least inter-slice routing to the ILA core.
Use "keep" attribute at the connection to ILA core. This will force the net to remain when the
design is placed and routed. This may affect design performance.