AR# 1270


XACT-CPLD: Using a guide (.GYD) file to define pin constraints for CPLDs


Keywords: pin-locking, cpld, cst, gyd

Urgency: Standard

General Description:
In the XACT-CPLD flow, a Constraint File (.CST) is only used to
control timing constraints. Placement constraints are not
recognized in a CST file.

Xilinx recommends that all placement constraints be put
in the source design file (either Schematic or Equation-based).
However, it is possible to place PIN assignments in a guide
file (.GYD), and have the software treat these as constraints.

The GYD file is really intended for guiding placement off a
previous implementation. However, with the current software,
pin assignments in the .GYD file and in the design file are
treated the same, and so it is possible to edit a
previously-generated .GYD file to add pin constraints as



XACT 6.0.1

How to lock pins using a .GYD file for CPLDs:

1. Fit the design (Implement from Design Manager).
This will automatically produce a file entitled <design>.gyd
and place it in your project directory under the correct

2. Edit this file to lock down pins. It looks something like:

with CLK and INPUT1 referring to I/O signals in the design.

In this case, CLK will be assigned to pin 20, and INPUT1 will
be assigned to pin 45.

If you are targetting one of the Grid-Array packages, then the
syntax will be like:

Where the signal CLK will be assigned to pin F3, and INPUT1
will be assigned to pin A12.

3. In the Design Manager in Windows, select Tools->FlowEngine.
In the Flow Engine select Setup->Advanced...
In the Flow Configuration box use the Browse option to select
the path to the .GYD file you just edited. Continue with
design implementation as usual.


The guide (.GYD) file is case sensitive in M1.3/M1.4 release.

AR# 1270
日付 10/07/2008
ステータス アーカイブ
種類 一般
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