entity LVDS_IOBUFDS is port (CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n: in STD_LOGIC; IODATA_p, IODATA_n : inout STD_LOGIC; Q_p, Q_n : out STD_LOGIC); end LVDS_IOBUFDS;
architecture BEHAV of LVDS_IOBUFDS is
component IBUFDS is generic (IOSTANDARD : string); port (I : in STD_LOGIC; IB: in STD_LOGIC; O : out STD_LOGIC); end component;
component OBUFDS is generic (IOSTANDARD : string); port (I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC); end component;
component IOBUFDS is generic (IOSTANDARD : string); port (I : in STD_LOGIC; T : in STD_LOGIC; O : out STD_LOGIC; IO: inout STD_LOGIC; IOB: inout STD_LOGIC); end component;
component IBUFGDS is generic (IOSTANDARD : string); port(I : in STD_LOGIC; IB: in STD_LOGIC; O : out STD_LOGIC); end component;
component BUFG is port(I : in STD_LOGIC; O : out STD_LOGIC); end component;
signal datain2 : std_logic; signal odata_out: std_logic; signal DATA_int : std_logic; signal Q_int : std_logic; signal CLK_int : std_logic; signal CLK_ibufgout : std_logic; signal Tin_int : std_logic;
begin UI1: IBUFDS generic map (IOSTANDARD => "BLVDS_25") port map (DATA_p, DATA_n, DATA_int);