General Description: When I synthesize an HDL-coded design with FPGA Express, the following warning (HDL-307) is reported:
"HDL-307: Warning: Latch inferred in design '***' read with 'hdlin_check_no_latch'."
How do I avoid this warning?
ソリューション
If there is a case statement or "if/else" in the code, and if all the possible conditions and states are not covered, a latch is being inferred. This causes the warning message.
- For a case statement, fill up all possible states by using "others" for VHDL or "default" for Verilog.
- For "if/else", ensure that there is an "else" for every "if" so that all cases will be caught.