When compiling the HDL code, you could receive the following error message:
"#ERROR: <vhdl_file>[<line_number>] No feasible entried for infix op: "=" "
The error message is valid. It specifies that you cannot compare two signals which are not the same data type. When using the "/=", both the signals should be of the same data type or this error message can be seen.
To work around this issue, recode the VHDL file such that the same data types are used for comparison purposes.