AR# 13132: 4.1i Modular Design - Assembly flow may alter the placement of BlockRAM during PAR
4.1i Modular Design - Assembly flow may alter the placement of BlockRAM during PAR
Keywords: BRAM, RAMB16, place, and, route, par
In 4.1i, modular design assembly flow is seen altering the BlockRAM placement. The BlockRAMs affected have constant (PWR or GND) drivers which are marked as active nets during active implementation. During assembly, all constants are rerouted so there is a mismatch that leads to unmatched BlockRAM between the guide file from PIM and the assembly from PAR. Hence, the BlockRAMs are assigned new placements.
To make sure this is the case, run assembly par as follow:
par -r -p <map.ncd>
Open the resulted NCD in FPGA Editor and search for unplaced components. This will tell you which components are not guided and will potentially get a new placement during assembly.
This issue has been fixed in the 5.1i software release. To workaround this, provide a LOC constraint on the BlockRAM.