We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13192

3.1i: Foundation Classic: Coregen: Fundational simulation of Delay Element causes:"Undetermined input pin state" errors.


Key words: Delay Element, Functional, Simulation, Undetermined, input, pin, state

Urgency: Standard

General Description: When attempting a functional simulation of the Delay Element component in Logic Simulator, the following template of error messages are found in the Logic Simulator pop-up window.

Signal : <instance_name / signal_name> undetermined input pin state.

The cause for these errors is due to the EDIF having a 3-input AND gate, only two of which are connected. Since the Logic simulator tool is a netlist simulator it is unable to account for the missing pin.
It is not know if this problem is due to optimization tools or if this is due to a bad EDIF written out.


What next:
1) Check point and timing simulation work fine. To do Check point simulation go to Tools --> Simulation/Verification --> Check Gatepoint Simulation Control and select NGD, NGC or NGA file you wish to simulate.

2) In 4.1i and 3.1i ISE Flow, using HDL,
Functional Simulation and Timing simulation work fine with Modelsim Simulator.

See solution 11267
AR# 13192
日付 08/19/2002
ステータス アーカイブ
種類 一般