We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13241

7.0 SYNPLIFY - How do I infer dynamically variable shift register LUTs (SRLs) for the Virtex architecture?


General Description: 

A dynamically variable shift register LUT (SRL) is an SRL that can vary the shift amount based on the address inputs of the SRL. (For more information on SRLs, please refer to the Libraries Guide at http://support.xilinx.com/support/library.htm.)

How do I infer a dynamically variable shift register LUT for the Virtex architecture?


The following example is taken from the Synplify Pro User Guide (C:\Synplicity\synplify_70\doc), pages 4-80: 


VHDL example: 


library IEEE; 

use IEEE.std_logic_1164.all; 


entity srltest is 

port ( inData: std_logic_vector(7 downto 0); 

clk, en : in std_logic; 

outStage : in integer range 3 downto 0; 

outData: out std_logic_vector(7 downto 0)); 


end srltest; 


architecture rtl of srltest is 


type dataAryType is array(3 downto 0) of std_logic_vector(7 downto 0); 

signal regBank : dataAryType; 




outData <= regBank(outStage); 


process(clk, inData) begin 


if (clk'event and clk = '1') then 

if (en='1') then 

regBank <= (regBank(2 downto 0) & inData); 

end if; 

end if; 


end process; 


end rtl;


The following example is taken from the Synplify Pro User Guide (C:\Synplicity\synplify_70\doc), pages 4-80: 


Verilog example: 


module test_srl(clk, enable, dataIn, result, addr); 


input clk, enable; 

input [3:0] dataIn; 

input [3:0] addr; 

output [3:0] result; 


reg [3:0] regBank[15:0]; 

integer i; 


always @(posedge clk) begin 


if (enable == 1) begin 


for (i=15; i>0; i=i-1) begin 

regBank[i] <= regBank[i-1]; 



regBank[0] <= dataIn; 





assign result = regBank[addr]; 



AR# 13241
日付 05/14/2014
ステータス アーカイブ
種類 一般