// D flip-flop always @(posedge CLK) Q_OUT <= D_IN;
endmodule
2
-- VHDL
library IEEE; use IEEE.std_logic_1164.all; library synplify; use synplify.attributes.all;
entity fast_ex is port (CLK : in STD_LOGIC; D_IN : in STD_LOGIC_VECTOR (3 downto 0); Q_OUT : out STD_LOGIC_VECTOR (3 downto 0)); attribute xc_props of Q_OUT : signal is "DRIVE=24"; end fast_ex;
architecture XILINX of fast_ex is
begin
-- D flip-flop process(CLK) begin if rising_edge(CLK) then Q_OUT <= D_IN; end if; end process;