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AR# 13457

3.x FPGA Express - How do I instantiate a black box component/module?

説明


General Description:

How do I instantiate a black box component/module?

ソリューション


If there is a black box component/module named "black_box_core", a component/module declaration and a component/module instantiation must be made inside the proper VHDL/Verilog code, which will incorporate the black box into the design.



For example if ports a, b, and c exist ("a" and "b" being inputs and "c" being an output), you should have something similar to the following HDL:



VHDL:



:

:

component black_box_core is

port (a : in std_logic;

b : in std_logic;

c : out std_logic);

end component;

:

:



U1: black_box_component

port map (a => sig1, b => sig2, c => sig3);





Verilog:



A module declaration consists of the module being declared with only the port listings and declarations. The module declaration can either be in a separate file or in the same file where the core is being instantiated.



module black_box_core (a, b, c)

input a, b;

output c;

endmodule



Verilog Instantiation:



:

black_box_core U1 (.a(sig1), .b(sig2), .c(sig3));

:
AR# 13457
日付 01/11/2012
ステータス アーカイブ
種類 一般
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