AR# 14424

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11.1 Timing Analyzer/NGDANNO - DDR clock-to-out times in timing simulation do not match Timing Analyzer

説明

DDR clock-to-out times in timing simulation do not match those in Timing Analyzer/TRACE. There is approximately a 400 ps difference between the timing report and the timing simulation when DDR output flip-flops are used. 

 

Which number is correct? How can I fix this?

ソリューション

The timing reported by the Timing Analyzer and TRACE static timing analysis tools is correct.

AR# 14424
日付 05/14/2014
ステータス アーカイブ
種類 一般
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