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AR# 14603

SIMULATION, DCM - CLKDV output aligns with the falling edge of CLK0 instead of the rising edge of CLK0

説明

The clock divide output (CLKDV) aligns with the falling edge of CLK0 instead of the rising edge of CLK0 (this has only been observed when the DCM reset pulse is asserted for less than one clock cycle).

ソリューション

To avoid this problem, always assert the DCM reset for more than one clock cycle.

AR# 14603
日付 05/14/2014
ステータス アーカイブ
種類 一般
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