When a timing-constrained design is synthesized through Synplify, Synplify changes the default OBUF primitives to faster versions in order to make the design meet timing. This can cause board issues for designers who are unaware that the changes took place.
To override the default behavior, set the "xc_auto_fast" attribute in the HDL code as follows:
architecture beh of top is
attribute xc_fast_auto : boolean;
attribute xc_fast_auto of beh : architecture is false;
module top (q, d, addr, we, clk) /*synthesis xc_fast_auto=0 */;