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AR# 14831

7.x Synplify - Virtex-II の同期乗算器 (MULT18X18S) を Synplify で推論する方法

説明

キーワード : Synplify, VHDL, Verilog, multiply, multiplier, MULT18X18, 乗算, 乗算器

重要度 : 標準

概要 :
Virtex-II の同期乗算器 (MULT18X18S) を Synplify で推論する方法について

ソリューション

1

Synplify での同期乗算器 - VHDL 例 :

(注 : Synplify 属性の syn_pipeline を使用する必要あり)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xcv2_mult18x18s is
port (a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
clk : in std_logic;
prod : out std_logic_vector(15 downto 0));
end xcv2_mult18x18s;

architecture arch_xcv2_mult18x18s of xcv2_mult18x18s is

signal reg_prod : std_logic_vector (15 downto 0);

attribute syn_pipeline : boolean;
attribute syn_pipeline of reg_prod : signal is true;

begin

process(clk) is begin
if clk'event and clk = '1' then
reg_prod <= a*b;
end if;
end process;

prod <= reg_prod;

end arch_xcv2_mult18x18s;

2

Synplify での同期乗算器 - Verilog 例 :

(注 : Synplify 属性の syn_pipeline を使用する必要あり)

module xcv2_mult18x18s (a,b,clk,prod);
input [7:0] a;
input [7:0] b;
input clk;
output [15:0] prod;

reg [15:0] prod /* synthesis syn_pipeline = 1 */;

always @(posedge clk) prod <= a*b;

endmodule
AR# 14831
日付 04/23/2007
ステータス アーカイブ
種類 一般
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