There are 2 ways in which XBLOX can be used in a design through Foundation VHDL:
1. Inference by XVHDL. 2. Instantiation by the user.
ソリューション
1
Instantiation of XBLOX ---------------------- XBLOX may be instantiated in the VHDL code. Since the XBLOX library is a library of "parameterizable" macrocells, the same component may be declared once with ports of variable width, and then instantiated multiple times with various portwidths and parameters, if necessary. As well as declaring ports, generics may also be declared and mapped to the instantiated component to attach parameters to the component.
XVHDL comes with an XBLOX library with component declarations for all XBLOX components. (Some GENERIC properties may be missing. If you need to use a GENERIC, such as STYLE, you can edit the XBLOX.VHD library to add the GENERIC).
-- Example of instantiating an ADD_SUB component from the -- XBLOX library.
library IEEE; use IEEE.std_logic_1164.all;
library xblox; use xblox.macros.all;
entity ADDER is port (A_IN, B_IN: in std_logic_vector (5 downto 0); CARRYIN, A_S: in std_logic; COUT: out std_logic; SUM: out std_logic_vector (5 downto 0)); end ADDER;
architecture XBLOX of ADDER is
begin U1: ADD_SUB generic map (STYLE => "ripple") --defines style as RIPPLE port map (A => A_IN, B => B_IN, C_IN => CARRYIN, ADD_SUB => A_S, C_OUT => COUT, FUNC => SUM); end XBLOX;
2
Inference by XVHDL ------------------ XVHDL can automatically infer the following XBLOX components: ADD_SUB COMPARE COUNTER ACCUM
The XBLOX synthesis compile option must be selected, and the operands must be VHDL signals or variables for XBLOX inference to occur. The following example shows code which will infer an XBLOX COUNTER component. This simple counter design can be found in the ACTIVE\VHDL\SAMPLES\PREP7 directory.
--Example of inference of Xblox COUNTER
library IEEE; use IEEE.std_logic_1164.all;
entity PREP7 is port(CLK, RST, LD, CE: boolean; D: integer range 0 to 65535; Q: buffer integer range 0 to 65535); end PREP7;
architecture BEHAVIOR of PREP7 is begin process (RST, CLK) begin if (RST) then -- Async Reset Q <= 0; else if (CLK and CLK'event) then -- Clock edge if CE or LD then -- use register clk enable if LD then -- Sync Load Q <= D; else Q <= Q + 1; end if; end if; end if; end if; end process; end BEHAVIOR;