AR# 15564


6.1i CPLD - Registers don't toggle in timing simulation


Problem Description:  

In functional simulation, registers toggle as expected. However, in timing simulation, all registers are stuck at 0.


For VHDL Simulation: 

During the first 100 ns, a reset pulse is active, which prevents any registers from functioning. This is used to simulate the "power-up" phase in which registers with initial values are set or cleared before entering user mode.


For Verilog Simulation: 

If you are using HDL Bencher (Test Bench Waveform) to create a testbench for the first time, ensure that you select the "PRLD" (preload) checkbox in the "Global Signals" section. Registers will not function while this PRLD signal is active. The default PRLD pulse is 20 ns.  


If you are not using HDL Bencher: 


The "glbl.v" file needs to be compiled and referenced when running the simulation, as it will execute the initialization of all the registers.  



vlog time_sim.v testbench.v c:/xilinx/verilog/src/glbl.v 

vsim -L simprims_ver testbench glbl 


5.2i and earlier: 

Add the following to your test fixture. 


reg PRLD;  

assign glbl.PRLD = PRLD; 


Then, force it High for 100 ns (arbitrary number) and leave it Low for the remainder of the simulation.

AR# 15564
日付 05/08/2014
ステータス アーカイブ
種類 一般
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