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AR# 1618

*Obsolete* 5200 Direct Connect

説明

Keywords: XC5200, direct_connects, CLB, IOBs

Urgency: Standard

General Description:
In order to increase the performance of an XC5200 design, there are routing resources called direct connects which connect an IOB to a neighboring CLB without going through regular routing paths. This would be the shortest routing delays that could occur for data entering the chip.

How do I enable the software to use the direct connects?

ソリューション

1

If all else fails, the brute force method of using direct connects is to hand route that particular portion using Editlca, a Xilinx Design Editor (XDE) program. Information on using XDE may be found in Chapter 9 of the Development System User Guide as well as Chapter 4 of the Development System Reference Guide Volume 3. Both are defaultly installed by the XACT 5.2.1/6.0.1 software and may be accessed from the Xilinx Online Docs icon from the XACTstep 6.0 group.

These manuals are also availible from the Xilinx FTP site :
http://www.xilinx.com/txpatches/pub/documentation/xactstep6/dsuser.pdf
http://www.xilinx.com/txpatches/pub/documentation/xactstep6/dsref3.pdf

2

There currently are no switches or attributes to specify the use of direct connects.

The easiest way to persuade the software to use direct connects is to place timespecs on the design paths you wish to use this routing resource. If the timepecs dictate the use of direct connects, the software will subsequently place and route the design accordingly.

For more information on using Timespecs, consult (Xilinx Answer1331), (Xilinx Answer 1069), and (Xilinx Answer 409).

Information may also be found in Chapter 4 of the Development System Refence Guide Volume 1, which is defaultly installed
with the XACT 5.2.1/6.0.1 software and is availible from the Xilinx Online Docs icons from the XACTstep 6.0 group.

This manual is also from the Xilinx FTP site at :
http://www.xilinx.com/txpatches/pub/documentation/xactstep6/dsref1.pdf

3

If you find timespecs are ineffective, the next best thing you can do is bring the mapped design into the XACT Floorplanner and place the logic/FF next to the corresponding IOB you wish to have the software route the direct connects. By grouping the logic with the IOB, the router is typically intelligent enough to realize it can use the direct connects.

If you need information on using the floorplanner, there is a tutorial that is defaultly installed by the XACT 5.2.1/6.0.1 software and may be accessed from the Learning Center icon located in the XACTstep 6.0 group. This Windows-based tutorial is also accessible from the Xilinx FTP site :
http://www.xilinx.com/txpatches/pub/documentation/tutorials/xacttut.zip

Further information on the floorplanner may be found in the Floorplanner Reference Guide which also may be accessed from the Xilinx Online Docs icon from the XACTstep 6.0 group.

This manual is also availible from the Xilinx FTP site at :
http://www.xilinx.com/txpatches/pub/documentation/xactstep6/floorpln.pdf
AR# 1618
作成日 08/31/2007
最終更新日 09/26/2005
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