UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1621

5.0, 5.1 PPR, XDELAY - Why timing/performance results differ in the two report files.

説明

Comparing the design performance information produced by PPR and the
performance report produced by XDELAY or Timing Analyzer show different
values for the same design.
Which report is accurate?

ソリューション

The reason these two reports can contain different performance
figures for the same design is because the performance values
produced by PPR is strictly an estimation while XDELAY produces
a true approximation of maximum design performance within
device specification.

The reason for this is to reduce compile times of the placement
and routing of the design. This saves you time during
intermediate revisions of the design. If a true approximation
of the design performance is desired, XDELAY may subsequently
be run on the placed and routed design for a more accurate
report of design timing.
AR# 1621
作成日 08/31/2007
最終更新日 03/22/2000
ステータス アーカイブ
タイプ ??????