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AR# 1626

Foundation Simulator: Unknown outputs on 3K VHDL/ABEL/schematic design


If your design meets ALL of the following criteria, you may
see X's (unknowns) in your Functional Simulation:

1. Target device XC3x00/A/L
2. Mixed-mode schematic and VHDL/ABEL
3. Design contains XBLOX components (XBLOX may be inferred by
the XVHDL compiler)

The reason the X's are appearing on the schematic is due to
EQN symbols being present in the simulation netlist. EQN's
are not simulatable.

The IMPROVEX program inserts these EQN symbols into the XNF

A functionally equivalent netlist (.XAS) is also created,
which uses standard gates instead of EQN's, and is normally
used for functional simulation.

In the case where a design contains XBLOX, and top-level
design file is a schematic, the XNF file, instead of the XAS
file, will be merged into the functional simulation netlist.
This means that the EQN symbols will still be present in the
simulated netlist, and therefore X's will appear.

There are a few ways to get around this problem.



Since IMPROVEX is the program that inserts the EQN's, you
can turn IMPROVEX off before performing functional

After functional simulation is complete, and you are ready
to implement the design, re-synthesize the VHDL with IMPROVEX
turned on.

To turn IMPROVEX off:
In the HDL Editor, choose Synthesis -> Options.
Deselect Improvex.


Make sure that there are no XBLOX components in the design.
This means having no XBLOX on the schematic, and also turning
off XBLOX in the Synthesis -> Options dialog (in the HDL
Editor) so that the XVHDL compiler will not infer XBLOX

You can turn off XBLOX inference just for the purposes of
functional simulation, and then turn it back on when you are
ready to implement the design with the XACT Design Manager.


You can manually replace the synthesized XNF file with the
XAS file. Rename the .XAS file to .XNF. The file which is
simulated will still be the .XNF, but now it will not have
EQN's in it.

If you backup the original XNF file, you can then restore it
when you are ready to implement the design. This eliminates
the need to re-synthesize the code.
AR# 1626
日付 04/03/2000
ステータス アーカイブ
タイプ 一般