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AR# 17374

3.1 System Generator for DSP - ".do" files generated for Verilog black boxes are incorrect

説明

Description:  

The ".do" files generated when "Create testbench" is used have the wrong compilation command for Verilog black boxes. 

 

The ."do" files contain "vcom -93 myfile.v" when instead they should have "vlog myfile.v". 

 

This causes errors in compilation in ModelSim.

ソリューション

To work around this issue, manually edit the compilation line for Verilog files. Remove "vcom -93" and replace with "vlog". 

 

This has been fixed in the software as of System Generator for DSP v6.1.

AR# 17374
日付 05/15/2014
ステータス アーカイブ
種類 一般
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