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AR# 17502

6.1i CPLDFit - VHDL/Verilog equations appear to be incorrect

説明

General Description: 

My equations for active low 3-state outputs are incorrect in VHDL and Verilog formats; the enable signal is inverted. 

 

Example: 

 

Given the following logic: 

dout <= din when (en='0') else 'Z' 

 

The resulting equation is: 

dout <= din when (en='1') else 'Z'

ソリューション

This is only a reporting bug that can be safely ignored; the proper logic is being implemented correctly in the device.

AR# 17502
日付 05/08/2014
ステータス アーカイブ
種類 一般
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