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AR# 17508

6.1i Clocking Wizard/ECS - A schematic symbol from an XAW or VHDL/Verilog instantiation template creates an incorrect STATUS bus width


General Description: 

When I generate a schematic symbol from an XAW file with the Clocking Wizard, a symbol is created with an 8-bit STATUS bus. The STATUS bus should be 3 bits or (2:0). As a result, an error occurs during synthesis.


This issue is scheduled to be fixed in the ISE 7.1i software release.

AR# 17508
日付 05/08/2014
ステータス アーカイブ
種類 一般