AR# 17568


LogiCORE SPI-3 (POS-PHY L3) v3.1 - Can the PL3 data bus width be configured as 8 bits as opposed to 32?


General Description:  

The PL3 spec allows for an 8-bit data bus mode. Can Xilinx PL3 core do this? 

The PL3 core currently can only be configured with a data width of 32 bits.  

(This is true for both version 2 and 3 of the core.)


If you need to have an 8-bit data bus, you can ground the unused inputs and leave the outputs floating.  


According to the PL3 spec, here is what changes:  

1. The data path is an 8-bit data path instead of 32.  

2. MOD is not required at all. 

3. Parity is calculated over only 8 LSB. 


So, you could use a 32-bit core. Always zero out the 24 MSB (that is, use only data [7:0], set data [31:8] = 0). Don't hook up the mod pins on the output, and statically drive them low on the input side.  


Because this PL3 core was not specifically built for an 8-bits wide core, it requires the equivalent amount of resources as the 32-bit core.

AR# 17568
日付 05/15/2014
ステータス アーカイブ
種類 一般
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