AR# 176

FPGA Configuration - Can CCLK run before data is sent?

説明

General Description:

Users who download bitstreams from a microcontroller may want

to give the FPGA a free-running clock that would also be used

as the configuration clock (CCLK). This may result in the FPGA

seeing extra CCLKs before the configuration data is sent.

The problem with this situation is that the FPGA keeps a

running tally of how many configuration clocks have been

received since power-up. This number is matched against the

length count in the bitstream to determine when configuration

has been completed. The length count in the bitstream will not

account for the extra configuration clocks; thus, when all

the data has been sent, the length count and FPGA internal

count will not match (the FPGA's internal counter will contain

a greater value than the length count). The result is that the

FPGA will continue to wait for data until it has been provided

with enough configuration clocks to force its internal counter

to wrap back around to zero, and then up to the number in the

bitstream length count. At this point, the FPGA would end

configuration and assert the DONE pin.

The symptoms of this problem are a device that will not

configure but gives no indication of an error (if the

microcontroller stops providing cclks after sending all the

data), or a device that takes an unusually long time to

configure (if the microcontroller continues to provide cclks

after sending all the data).

Express Mode will ignore the CCLKs if the CS1 pin is LOW.

ソリューション

There are three resolutions.

Re-assert the PROG pin such that there are no more than four

(4) CCLKs after the rise of INIT and the start of the

configuration data. The configuration data starts with a byte

of dummy '1' fill bytes. These may also be trimmed to lessen

the number of extra CCLKs.

Modify the 24 bit length count number after the preamble in the

Bitstream Header to account for the extra CCLKs.

After downloading the bitstream, send the extra CCLKs required

to roll over the internal counter and count up to the length

count again (~18,000,000 CCLKs).

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AR# 176
日付	09/04/2011
ステータス	アーカイブ
種類	一般

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AR# 176

FPGA Configuration - Can CCLK run before data is sent?

説明

ソリューション