We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17891

3.2 EDK "proc_sys_reset_v1_00_a" - Faulty power-on reset condition logic


Urgency: Hot

General Description:

The "proc_sys_reset_v1_00_a" core has faulty power-on reset logic. Affected designs appear to be held in reset after the power-on state.


The work-around is to modify the "lpf.vhd" file located here:


Add the following lines in the component declaration before the begin line (line 153):

-- added code below

attribute INIT : string;

attribute INIT of POR_SRL_I : label is "FFFF";

-- added code above

begin ...

This will be fixed in the next release of the EDK.
AR# 17891
日付 07/26/2011
ステータス アーカイブ
種類 一般