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AR# 18291

LogiCORE SPI-4.2 (POS-PHY L4) - Dual Core Implementation Guide (full-duplex): Is it possible to implement two PL4 cores in a single FPGA?


Is it possible to implement two SPI-4.2 cores into a single FPGA?


If you are targeting Virtex-4 series of design, please refer to the Data Sheet and User Guide of SPI-4.2 v7.x series. 


For Virtex-II and Virtex-II Pro series, the Xilinx SPI-4.2 Core has fixed pin-out for the SPI-4.2 Interface; therefore, unique pin-out and UCF files are needed for each core. Hence, you will need to generate a core with a unique component name for each instance of the core. Xilinx currently offers dual-core solutions for the following selected device and package combinations: 



2v6000-FF1517 (-4=640Mbps, -5=700Mbps) in Static Alignment 

2v6000-FF1152 (-4=640Mbps, -5=700Mbps) in Static Alignment 

2v6000-FF1152 (-5=700Mbps, -6=800Mbps) in Dynamic Alignment 


Virtex-II Pro  

2VP30-FF1152 (-5=700Mbps, -6=700Mbps, -7=700Mbps) Static Alignment 

2VP30-FF1152 (-5=700Mbps, -6=800Mbps, -7=900Mbps) Dynamic Alignment 


Please contact your local FAE to obtain the SPI-4.2 Dual Core Implementation Guide that is available on Xilinx Sales Partners Web.  


Please also refer to (Xilinx Answer 18316) regarding Input Clock, BUFGMUX, and DCM placement issues.

AR# 18291
日付 05/16/2014
ステータス アーカイブ
種類 一般