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AR# 18292

10.1 Timing, PAR - Tools report an extra "bypass" path through the IOB for PCI versus LVDS (Tiofoi)


My design is a simple circuit with an IOB that utilizes an output FF, IOBUF PCI, and an input FF. The timing tools analyze a path from the output FF through IOBUF PCI to the input FF. However, if I change the IOSTANDARD attribute to another value (such as LVTTL), TRACE does not show a path from the output FF through IOBUF LVTTL to the input FF.  


Why does changing the IOSTANDARD affect how the tools analyze paths in the IOB?


The cell model has special circuits for I/O components in which the output buffer input signal can bypass the pad RC delay by going directly to the input side. However, this bypass path only exists under special circumstances. The tools use the following rules to determine if this bypass path should be analyzed:  



- the delay element has no bearing on the pad bypass feature 

- component must have both input and output buffers to use pad bypass 

- GTL flavors never use pad bypass 

- PCI flavors always use pad bypass 

- except for PCI, 3-state output buffers never use pad bypass 

- except for GTL, regular output buffers always use pad bypass 


NOTE: Standards like GTL (and GTLP) are single-ended driver standards.

AR# 18292
日付 05/16/2014
ステータス アーカイブ
種類 一般