Prior to the 1.3.2 release of the RapidIO LogiCORE Physical Layer, the example transmit clocking module, tx_clocking.v, required a 125 MHz input clock. This clock is sent to the transmit DCM and multiplied by 2 and divided by 2 to get a 250 MHz and 62.5 MHz clock. The CLK2X output of the DCM is used to clock the feedback of the DCM. The DCM will not lock when using this method.
For general information on this issue, please refer to (Xilinx Answer 18343).
As of release 1.3.2, Xilinx recommends users input a 250 MHz system clock for the generation of the 250 MHz and 62.5 MHz transmit (Tx) clocks. A module, tx_clocking.v, is provided with the Physical Layer RapidIO LogiCORE. In this module, a DCM is used to generate the 250 MHz RapidIO interface transmit clock and the 62.5 MHz user transmit clock. By inputting a 250 MHz clock to the Tx DCM, the CLK0X output is placed on a GCLK net and used for the RapidIO Tx interface. This CLK0X output can then also be used to clock the feedback of the DCM.
If it is necessary to input a 125 MHz system clock to generate the 250 MHz and 62.5 MHz clocks, then users must take care not to use the CLK2X output of the DCM to clock the DCM feedback. It is recommend that if the design already uses the CLK0X output of the DCM, that it is used to clock the feedback of the DCM.
If the CLK0X output is not being used, and a BUFG resource is available, please route the 0X output of the DCM through the BUFG and use this to clock the feedback of the DCM.
If no BUFG resources are available and it is necessary to have a 125 MHz input system clock, please contact Xilinx Technical Support (http://www.xilinx.com/support/services/contact_info.htm) for alternate solutions. Please refer this solution number, 18476, to the engineer helping you.