We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18575

LogiCORE XAUI v4.0 - Release Notes


General Description:  

This Answer Record contains the Release Notes for the XAUI v4.0 stand-alone core.


XAUI v4.0 


Software Requirements 


ISE 6.1i with Service Pack 3 and IP Update #1 or newer 


New Features in v4.0 

- Added support for ISE 6.1i software. 

- XAUI core can now be implemented in a XC2VP4 device. 

- Added additional details to the data sheet regarding compliance of state machines and the use of the MGT's Rx Elastic Buffer. 

- Updated the ENMCOMMAALIGN and ENPCOMMAALIGN logic, following the current recommendation in the RocketIO User's Guide. 


Bug Fixes in v4.0 

- Added "async_reg" attribute to cover cross-clock registers to prevent back-annotated simulation issues. 

- MDC is used to generate enable pulses for the management block which fixes a timing warning on this constraint. 

- Changed the implementation of BREFCLK from an IBUFG to an IBUFGDS according to recommendations in the RocketIO User's Guide. 

- Fixed an MDC clock-crossing issue caused by MDC being asynchronous to the core clock. 


Known Issues 

XAUI v4.0 core cannot be generated in Linux.  

- This was fixed in 6.2i. To work around the issue, generate the core in Solaris or on a PC and then implement the design on Linux. 


The XAUI v4.0 core cannot be generated with a Component Name of "xaui_core" in COREGen; doing so causes synthesis to fail in XST.  

- Refer to (Xilinx Answer 18747) for more information. 


In the XAUI v4.0 core, the MDIO interface of the XAUI block does not work properly. 

- To work around this issue, please install the patch below and regenerate the core. For more information, please see (Xilinx Answer 19392)




To resolve the issues listed in (Xilinx Answer 19392), apply the following patch to the 6.1.03i IP Update #1 or 6.2i (any service pack) installation: 



Install the patch as follows: 

1. Unzip the contents of the ".zip" file or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.  



Determine the Xilinx installation directory by typing the following at the command prompt: 

"echo %XILINX%" 


UNIX or Linux 

Determine the Xilinx installation directory by typing the following: 

"echo $XILINX" 


NOTE: You might need to have system administrator privileges to install the patch.  


2. After installing the patch, regenerate the Gigabit Ethernet MAC core from the CORE Generator. The core produced will contain the fix.

AR# 18575
日付 05/16/2014
ステータス アーカイブ
種類 一般