AR# 1863


Back-Annotation Timing Data May Contain Overly Conservative Values for the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical Post-layout Simulation Occurs When NGDAnno Is Called Without a Reference to the NGM File.


Platform: All
Architecture: XC4000E -2 and -3
Design Step: NGDAnno and Post-Layout Timing Simulation
Reference Number: 11562
The back-annotation timing data for input flip-flops and latches with the NODELAY attribute may contain PAD-to-IOB-IK-pin setup requirements that are 0.1ns (TTL mode) to 1.6ns (CMOS mode) too great. NGDAnno will issue a warning of the following type whenever it detects that a conservative value is being assigned to an IOB flip-flop/latch setup field:
WARNING:0 - Negative setup value of -1590 on block
MY_IOB/INBLOCK/IN_LATCH/LATCH, pin IN will be set to zero.
block name is of the form "iob_name/INBLOCK/IN_LATCH/
..." or "iob_name/INBLOCK/INFF/..." The pin name "IN" indicates
that the setup check on the data input pin is the affected cell. Setup times are reported in picoseconds.


Setup violations that occur during timing simulation should be investigated to determine whether they fall within these conservative time-windows. If so, they may safely be ignored. For example, assume that NGDAnno had issued the warning shown above. If your simulator reports a setup violation of 900ps at the latch MY_IOB/INBLOCK/IN_LATCH/LATCH, it may safely be ignored because 900ps is less than the 1590ps mentioned in the warning.
AR# 1863
日付 10/01/2008
ステータス アーカイブ
種類 一般
People Also Viewed