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AR# 18643

6.1 System Generator for DSP and Synplify 7.3.4 - Why do I get simulation mismatches when I use the retiming option for the Delay Block and Synplify 7.3.4?

説明

General Description: 

Why do I get simulation mismatches when I use the retiming option for the Delay Block and Synplify 7.3.4? 

 

The problem is that the initial values of the delay registers are expected to be all zeros. 

When the retiming is selected on the delay block, the registers are pulled into the logic that precedes it and the initial values of the registers are no longer zero.

ソリューション

The problem has been fixed in Synplify 7.5.1.

AR# 18643
日付 05/16/2014
ステータス アーカイブ
種類 一般
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