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AR# 18666

5.1i/6.1i COREGen Bus Mux V6.0 - Simulating the MUX_BUS Core in Verilog simulation gives incorrect results

説明


General Description: 
When the C_MUX_BUS_V6 Core is used in Verilog functional simulation, the results that are produced are not functionally correct. Why is this?

ソリューション


The problem is in the Verilog behavioral model. When using blocking statements instead of non-blocking statements, the simulation does not behave as expected. 
 
Work-around: 
 
Open the file: 
 
$XILINX/verilog/src/XilinxCoreLib/C_MUX_BUS_V6_0.v 
 
Go to line 305 and make the following change: 
 
Change the lines 
 
From: 
 
if(intEN === 1'b0) 
intO = #1 `allmyZs; 
else if(intEN === 1'bx) 
intO = #1 `allmyXs;  
 
To: 
 
if(intEN === 1'b0) 
intO <= #1 `allmyZs;  
else if(intEN === 1'bx) 
intO <= #1 `allmyXs;  
 
This problem will be fixed in V7.0 of the core.
AR# 18666
日付 05/16/2014
ステータス アーカイブ
種類 一般
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