When running a Modular Design through assembly, PAR gives the following error:
"ERROR:Place:44 - The global clocks x (BUFGMUX1S) and y (BUFGMUX1P)
are locked into a primary / secondary site pair. It is impossible to route all of
the clock loads for both of these clocks using the global clock routing resource."
What does this error mean?
This placer error can be caused by clock resource contention during assembly. In Modular Design, it is recommended that all clocks are kept at the top level, rather than in a module, to avoid this type of resource contention.